(1) Field of the Invention
The present invention relates to a device and a method for determining an overdrive period used in a semiconductor device. For example, it is applied to a sense amplifier circuit in a semiconductor memory device like DRAM (Dynamic Random Access Memory).
(2) Description of the Related Art
Densities of DRAMs are increased, and memory capacities are further increased. In this state, it is necessary for DRAM to enhance speed and to reduce power consumption.
By driving DRAM at a low voltage, reduction in power consumption can be attained. However, when DRAM is driven at the low voltage, there arises a problem where the amplifying rate of the sense amplifier becomes slow and the operating rate of DRAM is slowed down. An overdrive technique has been proposed as a technique for operating the sense amplifier at a low voltage and at high speed. The overdrive technique is that, for example, a high voltage (such as power source voltage VDD) is temporarily applied to a common driving line in the sense amplifier to enhance the current driving capability of MOS, thereby making the amplifying operation of the sense amplifier faster.
However, in the method that carries out the amplifying operation in the sense amplifier at high speed according to the above-described overdrive technique, the following problems arise depending on the setting of the overdrive period, namely, the period for which power source voltage VDD is applied.
For example, in a case of performing an overdrive in which, after applying external power source voltage VDD to the common driving line in the sense amplifier, dropped voltage (internal voltage) VDL (<VDD), namely, the dropped external power source voltage is applied to the common driving line; when the overdrive period is long, excessive overdrive is performed and the internal power source voltage for the array exceeds dropped voltage VDL to cause an excessive boost. To the contrary, when the overdrive period is short, no sufficient overdrive is performed. Accordingly, there is a problem that timing to make a p-channel MOS transistor (or n-channel MOS transistor) in the sense amplifier ON is delayed and data in a memory cell cannot be read accurately.
Therefore, the overdrive period control device capable of preventing excessive overdrive has been proposed (refer to Japanese Patent Laid-Open Nos. 9-120675 and 10-242815). The control device is provided with an inverter using external power source voltage VDD as an operating voltage as delay means for specifying the overdrive period. The inverter has the property in which the higher the operating voltage is, the shorter the transient response characteristic is. According to this inverter property, when external power source voltage VDD is high, the overdrive period is short and, on the contrary, when external power source voltage VDD is low, the overdrive period is long. Control of the overdrive period using the inverter property in this way prevents excessive overdrive.
However, the following problems arise in the conventional overdrive period control device described in Japanese Patent Laid-Open Nos. 9-120675 and 10-242815.
Generally, the operating range of general-purpose DRAM is set to 3.3V±0.3V for a power source voltage of 3.3V and to 5V±0.5V for a power source voltage of 5V. Therefore, preferably, the characteristic of the overdrive period control device, specifically, the adjustment range of the overdrive period using the inverter property is set within the operating range thereof, as appropriate, however, such a adjustment function have not been provided yet. Usually, the inverter property is set so that the overdrive period can be sufficiently controlled at the low side of power source voltage VDD within the operating range of a product. In DRAM that is set like this, at the high side of power source voltage VDD within the operating range, the adjustment range of the overdrive period using the inverter property is small. Therefore, there are some cases where the overdrive period is not adjusted sufficiently.
As described above, the conventional overdrive period control device has a problem in that the overdrive period cannot be adjusted sufficiently depending on setting of the inverter property because the inverter property is dependent on the power source voltage. To improve general versatility, it is desirable that the overdrive period can be sufficiently adjusted over the operating range of the product.
Further, when the driving voltage for the inverter is set as another power source voltage separately from the external power source voltage, namely, the second internal power source voltage which is the dropped external power source and is different from dropped voltage VDL, the control range of the overdrive period can be maintained constant regardless of the external power source voltage. However, it is difficult to provide a circuit for generating the second internal power source voltage like this in DRAM that will have improved designs and lower driving voltages recently.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.